Consumers are increasingly demanding both faster and smaller electronic products. The use of PCBs has grown enormously as new electronic applications are marketed. A PCB is formed by laminating a plurality of conducting layers with one or more non-conducting layers. As the size of a PCB shrinks, the relative complexity of its electrical interconnections grows.
A plated via structure is traditionally used to allow signals to travel between layers of a PCB. The plated via structure is a plated hole within the PCB that acts as a medium for the transmission of an electrical signal. For example, an electrical signal may travel through a trace on one layer of the PCB, through the plated via structure's conductive material, and then into a second trace on a different layer of the PCB.
Unfortunately, due to limitations within the prior art, the plated via structure may be longer than necessary to perform the function of electrical connectivity. For example, the plated via structure may extend completely through the PCB but only connect two traces on two proximate adjacent layers. As a result, one or more stubs may be formed. A stub is excessive conductive material within the plated via structure which is not necessary to transport the electrical signal.
When a high speed signal is transmitted through the plated via structure, a “stub effect” may distort the signal. The stub effect is a result of the useless excess conductive material present within the plated via structure. The stub effect occurs when a portion of the signal is diverted away from the trace connections and into one or more stubs of the plated via structure. The portion of the signal may be reflected from the end of the stub back toward the trace connections after some delay. This delayed reflection may interfere with signal integrity and increase, for example, the bit error rate of the signal. The degenerating effect of the stub effect may increase with the length of the stub. As much as 50% of signal attenuation at signals running at 10 Gigabits per second may be due to the stub in the plated via structure. Via structures with short stubs can be manufactured but require sequential processing, which increases costs substantially.
FIG. 1 is an illustration of a PCB 100 with a plated via structure 110 and a stub 170 in the prior art. The PCB 100 comprises conducting layers 130 separated by nonconductive dielectric layers 120. Typically, the plated via structure 110 includes a barrel (i.e., shaft of the via structure) that is cylindrical in shape and is plated with a conductive material 180. The plated via structure 110 allows an electrical signal 160 to transmit from a trace 140 on a first conducting layer 130 of the PCB 100 to a trace 150 on a second conducting layer 130. The stub 170 of the plated via structure 110 is the unnecessary portion of the plated via structure 110, which may create the stub effect.
FIG. 2 is an illustration of the PCB 100 with the plated via structure 110 after the stub 170 (shown in FIG. 1) has been removed by a mechanical drill process called backdrilling in the prior art. Backdrilling the unnecessary portion of the plated via structure 110 to reduce or remove the stub 170 is one method to reduce the stub effect. Backdrilling is a viable alternative to sequential layer processing but has limitations. Typically, a drill bit which has a larger diameter than via structure 110 backdrills the stub 170 thereby removing a portion of the unnecessary excess conductive material of the plated via structure 110. A backdrilled hole 200 is created once the drill bit removes a portion of the stub 170 from the plated via structure 110. The drill bit is commonly a carbide drill bit in a computer numerically controlled (CNC) drill machine. As a result of backdrilling, the portion of the stub 170 of the plated via structure 110 is removed, thereby reducing, but not completely eliminating, parasitic capacitance, parasitic inductance, and time delay, which may interfere with signal integrity.
In most cases, design concessions need to be made to allow for deviations in the accuracy of the drilling equipment. If the backdrilling is inaccurate (e.g. too deep), then a functional portion of the plated via structure 110 may be removed and the PCB 100 may be ruined. If the backdrilling is too shallow or off center, then the stub effect will remain. As a consequence, a new PCB 100 must be reconstructed and backdrilled. Thus, yields are reduced and costs are increased.
The backdrilling process is also limited in the tolerances that can be reliably held. Backdrilling is typically only controllable to a depth tolerance of +/−5 mils. In many cases, further design concessions need to be made due to limitations in the strength and consistency of the layers to allow for variations in the placement, width, and direction of drilling.
Yet another limitation is that many designs require the backdrilling of multiple plated via structures 110 where the stubs 170 may be at different depths. This requires specialized programming of the drill tool files, which takes time and money to produce.
Further, backdrilling multiple plated via structures 110 typically is a serial process, so that the time needed to backdrill the PCB 100 increases with the number of stubs 170. If any one of the stubs 170 is drilled improperly, the PCB 100 may be ruined. Therefore, backdrilling a number of stubs 170 increases the probability of damage to the PCB 100.
Another limitation is that many designs also require stubs to be removed from both surfaces of the PCB 100. This requires that the PCB 100 be reoriented during the backdrilling process, which further takes time, requires additional programming, and adds potential error to the accuracy of the backdrilling process.
On the other hand, backdrilling would not change used space in the PCB compared with non-backdrilled plated through hole (PTH) structures. That is, the backdrill technique is not a solution PCB density enhancement which is demanded by the market.
The sequential lamination process is a solution for this market demand. It allows for the creation of buried via hole (BVH) and interstitial via hole (IVH) structures in the PCB which achieves a zero length stub. However, the sequential lamination process exponentially increases the cost of the PCB due to its long process and technical difficulties. Additionally, the sequential lamination process involves an increased risk of short and long term reliability degradation of the PCB.